Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An efficient compactor for 45° layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A fully automatic hierarchical compactor
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An Implementation of Tarjan's Algorithm for the Block Triangularization of a Matrix
ACM Transactions on Mathematical Software (TOMS)
On Algorithms for Obtaining a Maximum Transversal
ACM Transactions on Mathematical Software (TOMS)
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
A new approach to hierarchical adaptation using sequence-control based on cell interactions
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
VLSI layout compaction using radix priority search trees
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On minimal closure constraint generation for symbolic cell assembly
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Hierarchical pitchmatching compaction using minimum design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A new hierarchical layout compactor using simplified graph models
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A compaction algorithm for non-convex polygons and its application
SCG '93 Proceedings of the ninth annual symposium on Computational geometry
MSTC: a method for identifying overconstraints during hierarchical compaction
DAC '93 Proceedings of the 30th international Design Automation Conference
Cell-based hierarchical pitchmatching compaction using minimal LP
DAC '93 Proceedings of the 30th international Design Automation Conference
Optimal graph constraint reduction for symbolic layout compaction
DAC '93 Proceedings of the 30th international Design Automation Conference
A compaction method for full chip VLSI layouts
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HIMALAYAS — a hierarchical compaction system with a minimized constraint set
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Cloning techniques for hierarchical compaction
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Practical method for obtaining a feasible integer solution in hierarchical layout optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
| Hi-index | 0.00 |
This paper describes a one-dimensional compactor which simultaneously compacts the contents of all cells of a layout hierarchy without changing the hierarchy. The compactor performs both compaction and wire length minimization hierarchically using the power of the Simplex method for linear programs. Compaction of arrays, compaction of overlapping cells, and symmetry preserving compaction are also handled, since these are special cases of layout hierarchies. Using dedicated Simplex algorithms for compaction and wire length minimization, a globally optimum result is produced quickly and efficiently without the use of protection frames or domains and terminals. The compactor corrects design rule violations, preserves wire widths, and maintains terminal connections automatically. It does not yet introduce jogs in wires automatically. Results are provided for a few CMOS modules, including a ROM and an SRAM core.