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DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
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ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
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Proceedings of the 1997 international symposium on Physical design
Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Application of automated design migration to alternating phase shift mask design
Proceedings of the 2001 international symposium on Physical design
A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
STI stress aware placement optimization based on geometric programming
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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Layout optimization is a powerful technique for design migration, circuit performance tuning and design for manufacturing. In this paper, we study the problem of layout optimization for the hierarchical circuits in modern VLSI designs which essentially can be formulated as the Integer Linear Programming(ILP) problem. Existing approaches are either unable to handle hierarchy, inefficient or failing to provide the feasible integer solutions for large scale hierarchical layouts. We present a practical method, IRLS algorithm (Iteratively Rounding and LP Solving) which consists of a proper rounding strategy based on the careful analysis of hierarchical layout constraints, to obtain a feasible integer solution in the constraint-based layout modification process, thus enabling efficient optimization for large scale hierarchical layouts, and specifically avoiding the need to use the general ILP solvers. Experimental results demonstrate the efficiency and effectiveness of the IRLS algorithm. Compared with the general ILP/MILP solver, the IRLS algorithm can obtain decent results with much less runtime (speed-up ranging from 4,000X to 360,000X). Compared with the two-step approach[2] on legalizing a set of large scale industry circuit layouts, the IRLS algorithm can provide much better solution (satisfying all abutment/alignment constraints that the two-step approach fails to meet).