Proceedings of the 14th ACM Great Lakes symposium on VLSI
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
Practical method for obtaining a feasible integer solution in hierarchical layout optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Electromigration (EM) is a major failure mechanism in today's deep-submicron VLSI circuits. It has become more so due to increasingly smaller circuit wires and higher current density. The most direct and effective method to reduce the EM susceptibility of a circuit is to increase the width of wires that have high current density. Wire widening in a layout implies that interacting layout elements need to be adjusted in order to accommodate the widened wires. In this paper, we study the problem of automatic widening of wires with high current density in a completed layout. We use the minimum layout perturbation criteria when adjusting the positions of layout elements to preserve as much structure of the layout as possible. We propose a fast heuristic based on a single error removal algorithm. Our experiments show that the fast heuristic is very suitable for widening wires to enhance EM reliability and the new algorithm is 4x-10x faster than a general purpose graph-based simplex (GBS) solver for the general minimum layout perturbation problem.