A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths

Authors:
Lih-Yang Wang;Yen-Tai Lai;Bin-Da Liu;Ting-Chung Chang
Affiliations:
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.
Venue:
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Year:
1993

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