Routing L-shaped channels in nonslicing-structure placement
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An efficient compactor for 45° layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Wirelength reduction by using diagonal wire
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Congestion reduction in traditional and new routing architectures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Channel routing in Manhattan-diagonal model
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor
ICCD '03 Proceedings of the 21st International Conference on Computer Design
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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This paper presents a diagonal routing method which is applied to an actual microprocessor prototype chip. While including the layout functions for the conventional Manhattan routing with horizontal and vertical directions, a new diagonal routing capability is added as one of the routing functions. With this enhancement, diagonal routing becomes an additional strategy for improving delays of critical paths in the microprocessor design. This method was applied to the prototype chip of the Fujitsu SPARC64 microprocessor with two CPU cores using 90nm process technology. By applying the diagonal routing to long distance nets, net length is reduced by 36% per net on average. When the diagonal routing is applied to a critical path, path delay is improved by as much as about 14 pico-seconds per net on a path. This improvement is more than the delay of a gate with no load. This prototype chip proved that our method was effective in reducing the total net length and improving path delays.