The lambda-geometry Steiner minimal tree problem and visualization
The lambda-geometry Steiner minimal tree problem and visualization
A fast and simple Steiner routing heuristic
Discrete Applied Mathematics - Special volume on VLSI
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Diagonal routing in high performance microprocessor design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architecture
IMCAS'09 Proceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems
WSEAS Transactions on Circuits and Systems
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We study the octilinear Steiner tree to evaluate the rectilinear Steiner tree based router. First, we give the worst and average case wirelength for rectilinear routing and octilinear routing for two terminals net. Next, we show the octilinear Steiner trees have smaller wirelength reduction for multiterminal net than that of rectilinear Steiner tree. Then, we propose an O(|V|+|E|) algorithm to construct an isomorphic octilinear Steiner tree from a rectilinear Steiner tree G = (V, E) and prove the wirelength of the isomorphic octilinear Steiner tree is the lower bound. In the end, we show two types of experiment of wirelength reduction results by using diagonal wire The octilinear Steiner tree reduces 9.201% and 6.63% of the wirelength over rectilinear Steiner tree on a set of nets generated at random and on 15 VLSI designs, respectively.