The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Constructing exact octagonal steiner minimal trees
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Wirelength reduction by using diagonal wire
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the λ-geometry plane
Proceedings of the 2006 international symposium on Physical design
Efficient obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 2007 international symposium on Physical design
A Novel Performance-Driven Topology Design Algorithm
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Timing-driven routing for FPGAs based on Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spanning graph-based nonrectilinear steiner tree algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO-aware obstacle-avoiding routing tree algorithm
WSEAS Transactions on Circuits and Systems
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This study formulates a novel timing-driven rectangular and non-rectangular obstacle-avoiding X-based Steiner minimal tree (TNOA-XSMT) problem. The problem is first studied in the literature, and solved by using a timing-driven routing algorithm. The algorithm, which handles both the rectangular and non-rectangular obstacles, minimizes the maximum source-to-terminal delay. A novel concept of incorporating the virtual nodes during the spanning graph construction is presented to minimize the total wire length. An extension is provided to explain how the algorithm handles the obstacles with any geometric shape. Moreover, an effective and efficient rerouting scheme is adopted to further reduce the delay. Rerouting reduces the maximum source-to-terminals delay by 49.1%, while increasing the additional total wire length by only 2.5%.