Efficient obstacle-avoiding rectilinear steiner tree construction

Authors:
Chung-Wei Lin;Szu-Yu Chen;Chi-Feng Li;Yao-Wen Chang;Chia-Lin Yang
Affiliations:
National Taiwan University, Taipei, Taiwan Roc;National Taiwan University, Taipei, Taiwan Roc;National Taiwan University, Taipei, Taiwan Roc;National Taiwan University, Taipei, Taiwan Roc;National Taiwan University, Taipei, Taiwan Roc
Venue:
Proceedings of the 2007 international symposium on Physical design
Year:
2007

Citing 8
Cited 17

Rectilinear shortest paths through polygonal obstacles in O(n(logn)2) time

SCG '87 Proceedings of the third annual symposium on Computational geometry
Introduction to Algorithms

Introduction to Algorithms
A solution to line-routing problems on the continuous plane

DAC '69 Proceedings of the 6th annual Design Automation Conference
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An-OARSMan: obstacle-avoiding routing tree construction with good length performance

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the λ-geometry plane

Proceedings of the 2006 international symposium on Physical design
Efficient Steiner tree construction based on spanning graphs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-performance routing at the nanometer scale

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree

Proceedings of the 2008 international symposium on Physical design
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction

Proceedings of the 2008 international symposium on Physical design
The coming of age of (academic) global routing

Proceedings of the 2008 international symposium on Physical design
MaizeRouter: engineering an effective global router

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Obstacle-avoiding rectilinear Steiner tree construction

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On improving optimization effectiveness in interconnect-driven physical synthesis

Proceedings of the 2009 international symposium on Physical design
High-performance obstacle-avoiding rectilinear steiner tree construction

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architecture

IMCAS'09 Proceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems
Timing-driven X-architecture routing tree construction among rectangular and non-rectangular obstacles

WSEAS Transactions on Circuits and Systems
Custom networks-on-chip architectures with multicast routing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree

Proceedings of the 2009 International Conference on Computer-Aided Design
Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Orthogonal hyperedge routing

Diagrams'12 Proceedings of the 7th international conference on Diagrammatic Representation and Inference
Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction

Proceedings of the International Conference on Computer-Aided Design
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach

Integration, the VLSI Journal

Quantified Score

Hi-index	0.01

Visualization

Abstract

Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph (OASG), this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any 2-pin net and many higher-pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works.