High-performance routing at the nanometer scale

Authors:
Jarrod A. Roy;Igor L. Markov
Affiliations:
The University of Michigan, Ann Arbor, MI;The University of Michigan, Ann Arbor, MI
Venue:
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Year:
2007

Citing 24
Cited 39

PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Introduction to Algorithms

Introduction to Algorithms
Improved global routing through congestion estimation

Proceedings of the 40th annual Design Automation Conference
Automated rip-up and reroute techniques

DAC '82 Proceedings of the 19th Design Automation Conference
Probabilistic congestion prediction

Proceedings of the 2004 international symposium on Physical design
Physical CAD changes to incorporate design for lithography and manufacturability

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Is probabilistic congestion estimation worthwhile?

Proceedings of the 2005 international workshop on System level interconnect prediction
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design

Proceedings of the 2005 international symposium on Physical design
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
True crosstalk aware incremental placement with noise map

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Post-routing redundant via insertion for yield/reliability improvement

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Highly scalable algorithms for rectilinear and octilinear Steiner trees

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
BoxRouter: a new global router based on box expansion and progressive ILP

Proceedings of the 43rd annual Design Automation Conference
On whitespace and stability in physical synthesis

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Efficient obstacle-avoiding rectilinear steiner tree construction

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Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space

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FastRoute: a step to integrate global routing into placement

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Wire density driven global routing for CMP variation and timing

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FastRoute 2.0: A High-quality and Efficient Global Router

ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability

ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Global routing by new approximation algorithms for multicommodity flow

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pattern routing: use and theory for increasing predictability and avoiding coupling

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Creating and exploiting flexibility in rectilinear Steiner trees

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Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement

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Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals

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Sidewinder: a scalable ILP-based router

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Issues in global routing

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The coming of age of (academic) global routing

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A new global router for modern designs

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability

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NTHU-Route 2.0: a fast and stable global router

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FastRoute3.0: a fast and high quality global router based on virtual capacity

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Multi-layer global routing considering via and wire capacities

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Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FastRoute 4.0: global router with efficient via minimization

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High-performance global routing with fast overflow reduction

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Robust layer assignment for via optimization in multi-layer global routing

Proceedings of the 2009 international symposium on Physical design
Diffusion-driven congestion reduction for substrate topological routing

Proceedings of the 2009 international symposium on Physical design
GRIP: scalable 3D global routing using integer programming

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Detailed-routing algorithms for dense pin clusters in integrated circuits

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Archer: a history-based global routing algorithm

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Exact route matching algorithms for analog and mixed signal integrated circuits

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The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)

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A multilevel congestion-based global router

VLSI Design
Effective congestion reduction for IC package substrate routing

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilayer global routing with via and wire capacity considerations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power-efficient multipin ILP-based routing technique

IEEE Transactions on Circuits and Systems Part I: Regular Papers
A parallel integer programming approach to global routing

Proceedings of the 47th Design Automation Conference
A pareto-algebraic framework for signal power optimization in global routing

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Integration, the VLSI Journal
Routing with graphene nanoribbons

Proceedings of the 16th Asia and South Pacific Design Automation Conference
The ISPD-2011 routability-driven placement contest and benchmark suite

Proceedings of the 2011 international symposium on Physical design
Efficient congestion mitigation using congestion-aware steiner trees and network coding topologies

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MGR: multi-level global router

Proceedings of the International Conference on Computer-Aided Design
Exploring high throughput computing paradigm for global routing

Proceedings of the International Conference on Computer-Aided Design
An auction based pre-processing technique to determine detour in global routing

Proceedings of the International Conference on Computer-Aided Design
New placement prediction and mitigation techniques for local routing congestion

Proceedings of the International Conference on Computer-Aided Design
Design-hierarchy aware mixed-size placement for routability optimization

Proceedings of the International Conference on Computer-Aided Design
Stability and scalability in global routing

Proceedings of the System Level Interconnect Prediction Workshop
GDRouter: interleaved global routing and detailed routing for ultimate routability

Proceedings of the 49th Annual Design Automation Conference
FastRoute: an efficient and high-quality global router

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CATALYST: planning layer directives for effective design closure

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A routing algorithm for graphene nanoribbon circuit

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Abstract

In this work we describe significant improvements to core routing technologies and outperform the best results from the ISPD '07 Global Routing Contest, as well as previous literature, in terms of route completion, runtime and total wirelength. In particular, our router, FGR, improves upon wirelengths produced by BoxRouter and MaizeRouter in March 2007 by 9.9% and 8.4%, respectively. Additionally, we reveal the mathematical basis of negotiated-congestion routing, offer comprehensive analysis of existing routing techniques and discuss several applications at the nanometer scale.