Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Gate Sizing to Eliminate Crosstalk Induced Timing Violation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Design & Test
A global router with a theoretical bound on the optimal solution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early probabilistic noise estimation for capacitively coupled interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven white space allocation for fixed-die standard-cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective free space management for cut-based placement via analytical constraint generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
Computational geometry based placement migration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Crosstalk-aware domino logic synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Evaluation, prediction and reduction of routing congestion
Microelectronics Journal
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Technology mapping with crosstalk noise avoidance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Crosstalk noise has become an important issue as technology scales down for timing and signal integrity closure. Existing works to fix crosstalk noise are mostly done at the routing or post routing stage, which may be too late. Since placement determines the overall routing congestion, which correlates with the coupling capacitance, which in turn correlates with the crosstalk noise, placement shall be a good level to do early noise mitigation. The only existing work for the crosstalk aware placement (to our best knowledge) is by Lou and Chen (2004), which uses the coupling capacitance map to guide placement. However, crosstalk is determined not only by the coupling capacitance, but also by many other factors, such as the driver resistance of the victim net and the coupling location (near source vs near sink coupling) (Cong et al., 2001). We introduce a concept of noise map which takes those factors into account. Guided by this accurate noise map explicitly, we propose an incremental placement technique to mitigate noise without disturbing the global placement order. Our incremental placement has two key steps, namely noise aware cell inflation and local refinement. Experimental results on industrial circuits show that our approach is able to reduce the number of top noise nets by 25% and improve the timing (300ps on the worst slack), with no wire length penalty or CPU overhead. Our incremental approach is also able to maintain the placement stability.