Aggressor alignment for worst-case coupling noise
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Proceedings of the conference on Design, automation and test in Europe
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A decoupling method for analysis of coupled RLC interconnects
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Incremental delay change due to crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Estimation of the likelihood of capacitive coupling noise
Proceedings of the 39th annual Design Automation Conference
Crosstalk noise estimation for noise management
Proceedings of the 39th annual Design Automation Conference
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Capturing crosstalk-induced waveform for accurate static timing analysis
Proceedings of the 2003 international symposium on Physical design
Efficient crosstalk noise modeling using aggressor and tree reductions
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Closed-Form Crosstalk Noise Delay Metrics
Analog Integrated Circuits and Signal Processing
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect design methods for memory design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog Integrated Circuits and Signal Processing
Analytical approach for testing linking-with-light circuits and systems
IMACS'08 Proceedings of the 7th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
WSEAS Transactions on Circuits and Systems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An analytical approach to dynamic crosstalk in coupled interconnects
Microelectronics Journal
Numerical analysis of electromagnetic fields in interconnecting grids
MINO'06 Proceedings of the 5th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using well-solvable quadratic assignment problems for VLSI interconnect applications
Discrete Applied Mathematics
Crosstalk in high-performance asynchronous designs
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Worst case crosstalk noise effect analysis in DSM circuits by ABCD modeling
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology under any specified input excitation. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques, such as transistor sizing, and layout techniques, such as wire ordering and wire width optimization to reduce crosstalk