Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Speed Digital Circuits
Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects
Microelectronics Journal
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of crosstalk noise in coupled RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.