Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Post global routing crosstalk risk estimation and reduction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Digital sensitivity: predicting signal interaction using functional analysis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Symbolic computation of logic implications for technology-dependent low-power synthesis
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
IBAW: an implication-tree based alternative-wiring logic transformation algorithm
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Algorithms and Data Structures in VLSI Design
Algorithms and Data Structures in VLSI Design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Minimizing Spurious Switching Activities in CMOS Circuits
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
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Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes the assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst- case noise pulse on the victim net that often leads to false noise violations. In this article we present a new approach that uses logic implications to identify the maximum set of aggressor nets that can inject noise simultaneously under the logic constraints of the circuit. We propose an approach to efficiently generate logic implications from a transistor-level description and propagate them in the circuit using ROBDD representations. We propose a new method for lateral propagation of implications and also show how tristate gates and high-impedance signal states can be handled using tristate implications. We then show that the problem of finding the worst-case logically feasible noise can be represented as a maximum weighted independent set problem and show how to efficiently solve it. Initially, we restrict our discussion to zero-delay implications, which are valid for glitch-free circuits, and then extend our approach to timed implications. The proposed approaches were implemented in an industrial noise analysis tool and results are shown for a number of industrial test cases. We demonstrate that a significant reduction in the number of noise failures can be obtained from considering the logic implications as proposed in this article, underscoring the need for false-noise analysis.