Transistor sizing for low power CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing in order to guarantee synchronously arriving signal slopes at the input of logic gates. Since the delay of a logic gate depends directly on transistor sizes, the variation of channel-widths and -lengths (W and L) allows to equalize different path delays without influencing the total propagation delay of the circuit. Unfortunately not only the delay, but also the total capacitance and the short-circuit power consumption of a circuit depend on the transistor sizes. In order to take this fact into account, the method is formulated as a multiobjective optimization problem, where the path delay differences and the power consumption are the design objectives. To achieve optimal results, transistor lengths have to be increased, which results in both increased gate capacitances and area. Splitting the long transistors counteracts this negative influence and reduces the power dissipated. Moreover, the so called "Zero-Delay" paths can be avoided by introducing additional delays.