IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Timing optimization through clock skew scheduling
Timing optimization through clock skew scheduling
Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections
Integration, the VLSI Journal
Power Distribution Networks in High Speed Integrated Circuits
Power Distribution Networks in High Speed Integrated Circuits
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact and efficient crosstalk estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Controlling the delay and the transition time of the clock signal in the presence of various noise sources, process parameter variations and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular, the effects of variations in power supply voltage (V DD), temperature, and gate oxide thickness (t ox) on the delay and the transition time of the clock signal are evaluated. Furthermore, the effects of crosstalk between an H-tree structure and other interconnect wires are investigated. Different scenarios of capacitive coupling along different spatial locations of an H-tree are considered. The effects of coupling on the propagation delay, the transition time, and the waveform shape of the clock signal are demonstrated.