Simulated annealing: theory and applications
Simulated annealing: theory and applications
The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
High level profiling based low power synthesis technique
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
An architectural power optimization case study using high-level synthesis
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Towards a global solution to high level synthesis problems
EURO-DAC '90 Proceedings of the conference on European design automation
A Bus Encoding Technique for Power and Cross-talk Minimization
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical estimation of signal transition activity from word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing with crosstalk constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A postprocessing algorithm for crosstalk-driven wire perturbation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coupling-aware high-level interconnect synthesis [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Postroute gate sizing for crosstalk noise reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect-aware low-power high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Intrabus crosstalk estimation using word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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On-chip signal crosstalk is a function of switching activity pattern, coupling parasitics, and signal timing.We propose a simulated annealing (SA)-based high-level synthesis algorithm for crosstalk activity minimization for a given data environment. We target bus-based architectures as the bus-lines have well-defined neighborhood (aggressors). Our objective is to minimize worst case crosstalk patterns by exploring synthesis solutions with correlations that do not result in such worst case patterns. Besides synthesis moves, we also incorporate bus re-ordering and data transfer invert encoding. Experimental results for design under resource as well as latency constraints are promising. For a set of nine DSP benchmarks we reduce up to 75% of bus lines that require no shielding lines. The results also show that the designs synthesized through the proposed framework have an average performance improvement by 23.5% compared to un-optimized designs.