An architectural power optimization case study using high-level synthesis

Authors:
Affiliations:
Venue:
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Year:
1997

Citing 0
Cited 4

A source-level dynamic analysis methodology and tool for high-level synthesis

ISSS '97 Proceedings of the 10th international symposium on System synthesis
High-level scheduling model and control synthesis for a broad range of design applications

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Matisse: An Architectural Design Tool for Commodity ICs

IEEE Design & Test
Simultaneous scheduling, allocation, binding, re-ordering, and encoding for crosstalk pattern minimization during high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Architectural power optimization offers significant power gains in addition to which can be obtained at higher and lower levels of abstraction. Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and quite behind the current needs of the industry as many portable computing and communication products and greener non-portable products are being introduced into the market. In this paper we describe an environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available. We also present the results and findings from experiments with a CCITT G.721 ADPCM Predictor design, which should benefit on-going research on automated solutions.