MIST—a design aid for programmable pipelined processors
DAC '94 Proceedings of the 31st annual Design Automation Conference
A source-level dynamic analysis methodology and tool for high-level synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
High-level scheduling model and control synthesis for a broad range of design applications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Design process model in the Yorktown Silicon Compiler
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An architectural power optimization case study using high-level synthesis
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Analysis of emerging core-based design lifecycle
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An ASIP design methodology for embedded systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Efficient integration of behavioral synthesis within existing design flows
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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As today's market conditions require design organizations to create products in shorter time, there is also a significant change in the product mix due to fast growing markets such as wireless, automotive, multimedia and network applications. The nature of the current market conditions forces design organizations to move into product areas in which they don't have past experience and to design products with higher complexity, lower power, higher performance, better reusability, and lower cost in shorter turn-around time. It is accepted that the traditional RTL design methodologies cannot sustain the needed productivity increase.Behavioral synthesis offers a methodology which promises significant productivity increase by raising the abstraction level of digital design. Behavioral synthesis is a process of mapping an algorithmic description of a computation into a Register-Transfer Level (RTL) implementation. This methodology includes creating an algorithmic behavior, scheduling, allocating resources, sharing resources, creating interconnect, mapping of the algorithmic behavior to structure (binding), and generating finite-state-machine (FSM). During scheduling the cycle-by-cycle execution of each algorithmic statement is decided. The numbers and types of functional units and registers are decided during resource allocation. Multiplexers, tristate drivers, and wires are created to route the values in the data path from their sources to their destinations during the interconnect creation. Finally, an FSM is generated to control data-path elements and the interconnect according to the schedule and bindings.