High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Superpipelined control and data path synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An effective power management scheme for RTL design based on multiple clocks
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
An architectural power optimization case study using high-level synthesis
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Synthesis-for-testability of controller-datapath pairs that use gated clocks
Proceedings of the 37th Annual Design Automation Conference
Matisse: An Architectural Design Tool for Commodity ICs
IEEE Design & Test
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This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly support a broad range of architectural design applications from datapath-dominated digital signal processing (DSP) to micro-processors/controllers and control-dominated peripherals, utilizing multi-phase clocking schemes, multiple threading, data-dependent delays, pipelining, and combinations of the above. The work presented in this paper is an enabling technology for high-level synthesis to go beyond traditional datapath-dominated DSP applications and to start becoming a viable and cost-effective design methodology for commodity ICs such as micro-processors/controllers and control-dominated peripherals.