High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Control optimization in high-level synthesis using behavioral don't cares
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Profile-driven program synthesis for evaluation of system power dissipation
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level scheduling model and control synthesis for a broad range of design applications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of controllers for full testability of integrated datapath-controller pairs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A multiple clocking scheme for low-power RTL design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Register transfer level power optimization with emphasis on glitch analysis and reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A method for high level synthesis-for-testability of controller-datapath pairs that use gated clocks is developed. It uses a register allocation technique that improves the observability of the controller through the datapath, and takes advantage of the unique testability properties of one-hot-encoded controllers. The resulting controller can be fully tested without isolating it from the system. Area, fault coverage, and power consumption are reported for three example circuits.