A scheme for overlaying concurrent testing of VLSI circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Synthesis for testability of large complexity controllers
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Increasing testability by clock transformation (getting rid of those darn states)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A distance reduction approach to design for testability
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An optimized testable architecture for finite state machines
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Synthesis of controllers for full testability of integrated datapath-controller pairs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis-for-testability of controller-datapath pairs that use gated clocks
Proceedings of the 37th Annual Design Automation Conference
Modeling and simulation of real defects using fuzzy logic
Proceedings of the 37th Annual Design Automation Conference
Detecting undetectable controller faults using power analysis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A bypass scheme for core-based system fault testing
Proceedings of the conference on Design, automation and test in Europe
Integrated test of interacting controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
1.3 Parallelism in Structural Fault Testing of Embedded Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Efficient On-line-Test and Back-up Scheme for Embedded Processors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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In systems consisting of interacting datapaths and controllersand utilizing built-in self test (BIST), the datapaths andcontrollers are traditionally tested separately by isolatingeach component from the environment of the system duringtest.This work facilitates the testing of datapath-controllerpairs in an integrated fashion.The key to the approach isthe addition of logic to the system that interacts with theexisting controller to push the effects of controller faults intothe data flow, so that they can be observed at the datapathregisters rather than directly at the controller outputs.Theresult is to reduce the BIST overhead over what is neededif the datapath and controller are tested independently, andto allow a more complete test of the interface between datapathand controller.Fault coverage and overhead resultsare given for four example circuits.