Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital design principles and practices
Digital design principles and practices
SWiTEST: a switch level test generation system for CMOS combinational circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Bridge fault simulation strategies for CMOS integrated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Neuro-fuzzy and soft computing: a computational approach to learning and machine intelligence
Neuro-fuzzy and soft computing: a computational approach to learning and machine intelligence
A course in fuzzy systems and control
A course in fuzzy systems and control
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An efficient CMOS bridging fault simulator: with SPICE accuracy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosing realistic bridging faults with single stuck-at information
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the traditional zero-resistance model is not sufficient. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate-level. Our method produces more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test pattern statistics for the ISCAS85 benchmarks.