High-performance computer architecture (2nd ed.)
High-performance computer architecture (2nd ed.)
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
IEEE Spectrum
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Graph Theory With Applications
Graph Theory With Applications
Microprocessor based testing for core-based system on chip
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
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We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.