High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.Fault Detection for Linear Analog Circuits Using Current Injection83590987abs.htm J. Velasco-Medina , Th. Calin, M. NicolaidisReliable Integrated Systems Group, TIMA/INPGA new test technique for linear analog circuits which employs current injection as input test stimulus is described. Our investigations have shown that current transitions resulting from a current injected on internal test points are significantly different for the fault free and faulty circuits. This can be used for fault detection purposes. In fact, the current injection as test input stimulus represents a powerfull alternative to the test approaches based on conventional voltage input stimulus. The new approach allows to improve the testability of various faults, which are difficult to detect or are untestable when using voltage-based test stimulus. In addition the technique has significant advantages for BIST testing purposes. The technique is illustrated by means of a modern opamp circuit and by considering catastrophic and gate-oxide-short (GOS) faults. RAM-Based FPGA's: A Test Approach for the Configurable Logic83590082abs.htm M. Renovell, J. M. PortalLIRMM-UM2J. FiguerasUPC DiagonalY. ZorianLogic Vision Inc.This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic Test Configurations to fully test the whole matrix of CLBs. In the proposed Test Configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of Test Configurations 8 is fixed and independent of the FPGA size.