Architectural partitioning for system level design
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A scheme for overlaying concurrent testing of VLSI circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synthesis of controllers for full testability of integrated datapath-controller pairs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Synthesis for testability of large complexity controllers
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A distance reduction approach to design for testability
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An optimized testable architecture for finite state machines
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Decomposition and factorization of sequential finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In systems consisting of interacting datapaths and controllers and utilizing built-in self test (BIST), the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This work facilitates the testing of datapath/controller pairs in an integrated fashion. The key to the approach is the addition of logic to the system that interacts with the existing controller to push the effects of controller faults into the data flow, so that they can be observed at the datapath registers rather than directly at the controller outputs. The result is to reduce the BIST overhead over what is needed if the datapath and controller are tested independently, and to allow a more complete test of the interface between datapath and controller, including the faults that do not manifest themselves in isolation. Fault coverage and overhead results are given for four example circuits.