A scheme for overlaying concurrent testing of VLSI circuits

Authors:
W.-B. Jone;C. A. Papachristou;M. Pereira
Affiliations:
Department of Computer Science, New Mexico Tech, Socorro, NM;Department of Computer Engineering and Science, Case Weatem Reserve University, Cleveland, OH;Department of Computer Science, New Mexico Tech, Socorro, NM
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

This paper presents a test scheduling method, called overlaying concurrent testing, for built-in testing of VLSI circuits. The scheme is based on a resource-conflict analysis of subcircuits and a scheduling algorithm. The algorithm fully exploits test parallelism by overlaying the test intervals of compatible subcircuits to test as many of them as possible concurrently. The technique is supported by a test hardware architecture whose design is well coordinated with the test scheduling leading to a considerable reduction of testing time, as demonstrated by simulation experiments.