A scheme for overlaying concurrent testing of VLSI circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATS '00 Proceedings of the 9th Asian Test Symposium
Power-Constrained Block-Test List Scheduling
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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Abstract: Mixed classical scheduling algorithms are proposed here to improve the test concurrency having assigned power dissipation limits. An extended tree growing technique is used together with these algorithms in order to model the power-constrained test scheduling problem. A sequence of list and distribution-graph based scheduling algorithms is adapted to tackle it. A constant additive model is employed for power dissipation analysis and estimation. Firstly, a list scheduling-like algorithm is run in order to achieve rapidly a test scheduling solution with a near-optimal test application time. Then the power dissipation distribution of this solution is balanced by applying a distribution-graph based scheduling algorithm. Test scheduling examples and experiments are used in order to assess the efficiency of this approach comparing to the other approaches proposed before.