High-performance computer architecture (2nd ed.)
High-performance computer architecture (2nd ed.)
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
IEEE Spectrum
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
1.1 Test methodology for embedded cores which protects intellectual property
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Graph Theory With Applications
Graph Theory With Applications
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Journal of Electronic Testing: Theory and Applications
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A concurrent testing method for NoC switches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
Wrapper and TAM co-optimization for reuse of SoC functional interconnects
Proceedings of the conference on Design, automation and test in Europe
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
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The purpose of this paper is to develop a global design fortest methodology for testing a core-based system in its entirety. This is achieved by introducing a “bypass” mode for each core bywhich the data can be transferred from a core input port to theoutput port without interfering the core circuitry itself. Theinterconnections are thoroughly tested because they are used topropagate test data (patterns or signatures) in the system. Thesystem is modeled as a directed weighted graph in which theaccessibility (of the core input and output ports) is solved as ashortest path problem. Finally, a pipelined test schedule is made tooverlap accessing input ports (to send test patterns) and outputports (to observe the signatures). The experimental results showhigher fault coverage and shorter test time.