Linear Dependencies in Linear Feedback Shift Registers
IEEE Transactions on Computers
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Mixed-Mode BIST Using Embedded Processors
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
IEEE Spectrum
Optimal hardware pattern generation for functional BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On the quality of accumulator-based compaction of test responses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.