Group Properties of Cellular Automata and VLSI Applications
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
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IEEE Transactions on Computers
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Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
A Method for Designing a Deterministic Test Pattern Generator Based on Cellular Automata
Journal of Electronic Testing: Theory and Applications
Von Neumann hybrid cellular automata for generating deterministic test sequences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
Evolving Cellular Automata for Self-Testing Hardware
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
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EDTC '96 Proceedings of the 1996 European conference on Design and Test
Cellular Automata for Generating Deterministic Test Sequences
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Implicit test pattern generation constrained to cellular automata embedding
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Cellular automata for deterministic sequential test pattern generation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Width Compression for Built-In Self Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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IEEE Transactions on Computers
Reliability considerations in mobile devices
Proceedings of the 3rd international conference on Mobile multimedia communications
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This paper proposes a new approach for designing a cost-effective, on-chip, deterministic, built-in, self-test generator. Given a set of precomputed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector generator (TVG) is synthesized to apply the given test set in a minimal test time. To achieve this objective, cellular automata (CA) structures have been used in which the rule space is not limited to the linear rules commonly used in CA studies recently. Based on some new notations and new formulations of CA properties, two techniques are developed to synthesize such a TVG which is used to generate an ordered/unordered deterministic test vector set. The resulting TVG is very efficient in terms of hardware size and speed performance, and is very regular and testable. Simulation of various benchmark combinational circuits has given good results when compared to alternative solutions.