Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
Exact solution of large-scale, asymmetric traveling salesman problems
ACM Transactions on Mathematical Software (TOMS)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers
ATPD: An Automatic Test Pattern Generator for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Deterministic Test Pattern Reproduction by a Counter
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Method for Designing a Deterministic Test Pattern Generator Based on Cellular Automata
Journal of Electronic Testing: Theory and Applications
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We propose an on-chip test pattern generator that uses a one-dimensional cellular automaton (CA) to generate either a precomputed sequence of test patterns or pairs of test patterns for path delay faults. To our knowledge, this is the first approach that guarantees successful on-chip generation of a given test pattern sequence (or a given test set for path delay faults) using a finite number of CA cells. Given a pair of columns (C/sub u/,C/sub v/) of the test matrix, the proposed method uses alternative "linking procedures" P/sub j/ that compute the number of extra CA cells to enable the generation of (C/sub u/,C/sub v/) by the CA. A systematic approach uses the linking procedures to minimize the total number of needed CA cells. Experimental results show that the hardware overhead is often reasonable. The performance of the scheme depends on an appropriate choice of linking procedures P/sub j/.