Generation of deterministic test patterns by minimal basic test sets
EURO-DAC '92 Proceedings of the conference on European design automation
IEEE Transactions on Computers - Special issue on fault-tolerant computing
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers
BIST hardware generator for mixed test scheme
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Cellular Automata for Generating Deterministic Test Sequences
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Implicit test pattern generation constrained to cellular automata embedding
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Cellular automata for deterministic sequential test pattern generation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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This paper presents a new approach for designing a built-in testpattern generator based on cellular automata (CA). Given a set ofprecomputed test patterns, a test pattern generator issynthesized to apply the given test set in a minimal test time. The CA design is based on a novel matrix representation methodthat permits the use of the complete rule space and not only theadditive rules. A synthesis tool has been developed to implementthis design method. This synthesis tool provides a VHDLdescription of the resultant generator, which facilitates itsintegration into other VLSI design tools. This design techniquehas been applied to the combinational ISCAS benchmark circuitsproviding good results in terms of design time, performance andtest time required by the generator.