Deterministic Test Pattern Reproduction by a Counter

Authors:
Dimitrios Kagaris;Spyros Tragoudas;Amitava Majumdar
Affiliations:
Electrical Engineering Dept., Southern Illinois University, Carbondale, IL;Computer Science Dept., Southern Illinois University, Carbondale, IL;Apple Computers Inc., 1 Infinite Loop, Cupertino, CA
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

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Abstract

We propose a very simple and fast CAD tool to check whether a binary counter can reproduce a predetermined set of test patterns in a reasonable time. We use provably good algorithms to do column merging, complementation and permutation of the columns of the test matrix so that the distance between the starting and the finishing vector in the corresponding counter is minimized. Experiments on various test sets on benchmark circuits show that a counter may constitute an efficient test--pattern generator mechanism.