Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
On the Use of Counters for Reproducing Deterministic Test Sets
IEEE Transactions on Computers
BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Sequence reordering to improve the levels of compaction achievable by static compaction procedures
Proceedings of the conference on Design, automation and test in Europe
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On the design of optimal counter-based schemes for test set embedding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test embedding with discrete logarithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Multiphase Test Set Embedding for Scan-based Testing
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Reliability considerations in mobile devices
Proceedings of the 3rd international conference on Mobile multimedia communications
An accumulator-based compaction scheme for online BIST of RAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
The test set embedding problem is typically formed as follows: Given an n-stage pattern generator and a test set, calculate the minimum number of steps that the generator needs to operate in order to generate all vectors in the test set. The cornerstone of a test set embedding technique is its embedding algorithm. An embedding algorithm, given an n-stage pattern generator initialized to a starting value and an n-bit target vector V, calculates the location of V in the generated sequence. In this paper, a novel algorithm is presented that calculates the location of a vector into a sequence generated by an n-stage accumulator accumulating a constant pattern. The time complexity of the algorithm is of the order {\bf O}{\rm (n)}. To the best of our knowledge, this is the first embedding algorithm of the order {\bf O}{\rm (n)} that has been presented in the literature. Experiments performed on well-known benchmark circuits reveal that complete test sets are embedded in sequences of practically acceptable length.