Test Set Embedding Based on Phase Shifters
EDCC-4 Proceedings of the 4th European Dependable Computing Conference on Dependable Computing
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
IEEE Transactions on Computers
Reseeding-Based Test Set Embedding with Reduced Test Sequences
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Efficient Multiphase Test Set Embedding for Scan-based Testing
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Reliability considerations in mobile devices
Proceedings of the 3rd international conference on Mobile multimedia communications
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
| Hi-index | 0.04 |
Counter-based mechanisms have been proposed for use in built-in test set embedding. A single counter or multiple counters may be used with one or multiple seeds. In addition, counters may be combined with ROM's. Each alternative design scenario introduces a difficult combinatorial optimization problem: minimization of the time required to reproduce the test patterns by an appropriate synthesis of the built-in test pattern generator. This paper presents fast synthesis techniques that result in almost optimal designs. For any given circuit, they efficiently determine whether counter-based schemes are applicable as built-in generators for a given circuit. The proposed techniques have been implemented and tested on the ISCAS'85 benchmarks. Comparative studies with a weighted random linear feedback shift register scheme show that counter-based designs may offer good hardware/time solutions