Reseeding-Based Test Set Embedding with Reduced Test Sequences

Authors:
E. Kalligeros;D. Kaseridis;X. Kavousianos;D. Nikolos
Affiliations:
University of Patras, Greece/ Research Academic Computer Technology Institute, Greece;University of Patras, Greece/ Research Academic Computer Technology Institute, Greece;University of Ioannina, Greece;University of Patras, Greece/ Research Academic Computer Technology Institute, Greece
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

Citing 8
Cited 3

On Using Twisted-Ring Counters for Test Set Embedding in BIST

Journal of Electronic Testing: Theory and Applications
Test vector decompression via cyclical scan chains and its application to testing core-based designs

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test Data Compression

IEEE Design & Test
Test application time and volume compression through seed overlapping

Proceedings of the 40th annual Design Automation Conference
An Efficient Seeds Selection Method for LFSR-based Test-per-clock BIST

ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
On the design of optimal counter-based schemes for test set embedding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set embedding for deterministic BIST using a reconfigurable interconnection network

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiphase BIST: a new reseeding technique for high test-data compression

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Efficient Multiphase Test Set Embedding for Scan-based Testing

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Simultaneous reduction in test data volume and test time for TRC-reseeding

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

A novel technique for reducing the test sequences of reseeding-based schemes is presented in this paper. The proposed technique is generic and can be applied to test set embedding or mixed-mode schemes based on various TPGs. The imposed hardware overhead is very small since it is confined to just one extra bit per seed plus one very small counter in the scheme's control logic, while the test-sequence-length reductions achieved are up to 44.71%. Alongwith the test-sequence-reduction technique, an efficient seed-selection algorithm for the test-per-clock, LFSR-based, test set embedding case is presented. The proposed algorithm targets the minimization of the selected seed volumes and, combined with the test-sequence-reduction technique, delivers results with fewer seeds and much smaller test sequences than the already proposed approaches.