Simultaneous reduction in test data volume and test time for TRC-reseeding

Authors:
Bin Zhou;Yi-Zheng Ye;Yong-Sheng Wang
Affiliations:
Harbin Institute of Technology, Harbin, China;Harbin Institute of Technology, Harbin, China;Harbin Institute of Technology, Harbin, China
Venue:
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Year:
2007

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Abstract

A novel technique for reducing the test data volumes and the test application time of reseeding based on Twisted-ring counters is presented in this paper. The proposed technique is generic and can be applied to test set embedding or mixed-mode schemes. The imposed hardware overhead is very small (only a small test control logic and three counters) since it is confined to just one extra bit per seed and a control word, named ORVECTOR, whose length is shorter than that of seed. The test-sequence-length-reduction technique requires 47% fewer test vectors for all ISCAS'89 benchmark circuits than of the original technique. Along with the test-sequence-length-reduction technique, a more efficient seed-selection algorithm targeting the minimization of the volumes of the selected seed for the test-per-clock, TRC-based, test set embedding case is presented. The seed-selection-algorithm requires 20% fewer seed for all ISCAS'89 benchmark circuits, because of the stored control word, requires 11% less the test-data storage that of the original technique. The proposed technique which combines the seed-selection-algorithm with the test-sequence-length-reduction scheme, delivers results with fewer seeds and much shorter test sequences than the already proposed approaches.