Simultaneous reduction in test data volume and test time for TRC-reseeding
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A test set embedding approach based on twisted-ring counter with few seeds
Integration, the VLSI Journal
Self-test techniques for crypto-devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added on system paths. Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity. Results are also shown for combining "state skipping" logic with observation point insertion to further reduce hardware overhead.