Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On Random Pattern Testability of Cryptographic VLSI Cores
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Empirical evidence concerning AES
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Securing Scan Design Using Lock and Key Technique
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
Some upper and lower bounds on the coupon collector problem
Journal of Computational and Applied Mathematics
Securing Scan Control in Crypto Chips
Journal of Electronic Testing: Theory and Applications
Circular BIST with state skipping
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Secure Scan: A Design-for-Test Architecture for Crypto Chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
A novel differential scan attack on advanced DFT structures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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This paper describes a generic built-in self-test strategy for devices implementing symmetric encryption algorithms. Taking advantage of the inner iterative structures of crypto-cores, test facilities are easily set-up for circular self-test of the crypto-cores, built-in pseudorandom test generation and response analysis for other cores in the host device. Main advantages of the proposed test implementation are an architecture with no visible scan chain, 100% fault coverage on crypto-cores with negligible area overhead, availability of pseudorandom test sources, and very low aliasing response compaction for other cores.