Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Self-test techniques for crypto-devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
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In this paper we show, that the statisticalproperties of cryptographic algorithms are the reason for theexcellent pseudorandom testability of cryptographic processor cores.The work is especially concerned with modern symmetric blockencryption algorithms and their VLSI implementations. For theexamination typical basic operations of these cryptographicalgorithms are categorized in classes and analyzed regarding theirpseudorandom properties. Based on the results the pseudorandomproperties of symmetric block ciphers can be determined by means ofdata flow graphs (DFG) and so-called predecessor operation lists.This is demonstrated with a paradigm algorithm, the symmetric blockcipher 3WAY. The results of the theoretical analysis lead to aso-called global BIST concept for cryptographic processor cores. Thisself-test approach is characterized by central pseudorandom patterngenerators and signature registers at the primary inputs and outputsof the cores. The global BIST is exemplarily applied to animplementation of the 3WAY algorithm. Finally, the quality of thedeveloped test approach is determined by fault simulations.