A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Handbook of Applied Cryptography
Handbook of Applied Cryptography
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Security Extension for IEEE Std 1149.1
Journal of Electronic Testing: Theory and Applications
Secure Scan Techniques: A Comparison
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
An Efficient Approach to Develop Secure Scan Tree for Crypto-Hardware
ADCOM '07 Proceedings of the 15th International Conference on Advanced Computing and Communications
IEEE Design & Test
Self-test techniques for crypto-devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan-based attack against elliptic curve cryptosystems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Secure and testable scan design using extended de Bruijn graphs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Scan-based attacks on linear feedback shift register based stream ciphers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Secure Scan: A Design-for-Test Architecture for Crypto Chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PUF-based secure test wrapper design for cryptographic SoC testing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Scan chains insertion is the most common technique to ensure the testability of digital cores, providing high fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data thus becoming a threat to system security. So far, advanced test structures used to reduce test costs (e.g., response compaction) and achieve high fault coverage (e.g., X's masking decoder) have been considered as intrinsic countermeasures against these threats. This work proposes a new generic scan-based attack demonstrating that these test structures are not sufficiently effective to prevent leakage through the test infrastructure. This generic attack can be easily adapted to several cryptographic implementations for both symmetric and public key algorithms. The proposed attack is demonstrated on several ciphers.