A new scan attack on RSA in presence of industrial countermeasures
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
PUF-based secure test wrapper design for cryptographic SoC testing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A novel differential scan attack on advanced DFT structures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
| Hi-index | 0.00 |
useful method for testing VLSI designs due to its high controllability and observability. However scan chains have recently been shown to pose security threat to cryptographic chips. Researchers have proposed various prevention architectures like scan tree followed by a compactor, locking and TAP architecture. But these solutions lead to huge hardware overhead and slow the process of testing. In this paper we propose a novel secured scan tree architecture which has very low gate overhead, high fault coverage and is amenable to fast online testing . Index Terms--Scan Chains, Security, Fault Coverage, Hardware Overhead, Controllability, Observability, Scan Tree