Secure Scan Techniques: A Comparison

  • Authors:
  • David Hely;Frederic Bancel;Marie-Lise Flottes;Bruno Rouzeyre

  • Affiliations:
  • ST Microelectronics, France;ST Microelectronics, France;Université Montpellier II, France;Université Montpellier II, France

  • Venue:
  • IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
  • Year:
  • 2006

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Abstract

Designing secure ICs requires fulfilling many design rules in order to protect access to secret data. However, these security design requirements may be in opposition to test needs and testability improvement techniques that increase both observability and controllability. Nevertheless, secure chip designers cannot neglect the testability of their chip; a high quality production testing is primordial to ensure a good level of security since any faulty devices could induce major security vulnerability. In this paper, we present different techniques securing the scan chain technique and compare them to point out their pros and cons.