Logic testing and design for testability
Logic testing and design for testability
Design and Test of an Integrated Cryptochip
IEEE Design & Test
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Easily Testable Sequential Machines with Extra Inputs
IEEE Transactions on Computers
Securing Scan Control in Crypto Chips
Journal of Electronic Testing: Theory and Applications
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
Partial Scan Approach for Secret Information Protection
ETS '09 Proceedings of the 2009 European Test Symposium
Secure Scan: A Design-for-Test Architecture for Crypto Chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Secured Flipped Scan-Chain Model for Crypto-Architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Secure scan design using shift register equivalents against differential behavior attack
Proceedings of the 16th Asia and South Pacific Design Automation Conference
STEP: a unified design methodology for secure test and IP core protection
Proceedings of the great lakes symposium on VLSI
A novel differential scan attack on advanced DFT structures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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In this paper, we first introduce extended de Bruijn graphs to design extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. Using the extended shift registers, we present a new secure and testable scan design approach that aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan registers to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. New concepts of scan security and scan testability are also introduced.