Simultaneous reduction in test data volume and test time for TRC-reseeding
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Investigating some special sequence lengths generated in an external exclusive-NOR type LFSR
Computers and Electrical Engineering
coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips
ACRI '08 Proceedings of the 8th international conference on Cellular Automata for Reseach and Industry
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new methodology to increase the encoding efficiency of test compression based on linear feedback shift registers (LFSRs) is proposed. The proposed method combines LFSR reseeding and bit fixing. Deterministic test patterns tend to have a biased probability of the logic value 1 or 0 at each primary input. If such biased inputs are fixed to the logic value 1 or 0 with some combinational logic, then the amount of data to be encoded by the LFSR will be considerably reduced. Additionally, in order to reduce the encoded data volume much further, a variable degree of the LFSR polynomial is employed. In the variable-degree LFSR scheme, a test cube with less specified bits is encoded with an LFSR polynomial of lower degree, while a test cube with more specified bits is encoded with an LFSR polynomial of higher degree. Experimental results for the larger ISCAS 89 benchmark circuits show that the proposed scheme can increase the encoding efficiency with little hardware overhead compared to previous schemes.