Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Proceedings of the conference on Design, automation and test in Europe
Increasing encoding efficiency of LFSR reseeding-based test compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a cellular automata based Built-in self-test (BIST) core design for a self testing System-on-Chip (SoC) is proposed. The objective of the core is to generate pseudo-random test patterns that are injected into the various IP cores within an SoC. The corresponding output patterns are compacted and analyzed for correctness, during the test mode of the SoC. The BIST core was tested on some synthetic SoCs built by integrating ISCAS 85 benchmark circuits. Considerable reduction in the total test time and area is noticed, compared to the corresponding non-BISTEDed SoCs.