Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Efficient Seed Utilization for Reseeding based Compression
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Compression-Driven Test Access Mechanism Design Approach
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe
coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips
ACRI '08 Proceedings of the 8th international conference on Cellular Automata for Reseach and Industry
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as the compression engine. All cores on the SoC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits from the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that tries to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time is minimized. Experimental results for both ISCAS circuits and industrial circuits show that optimal test application time, which is determined by the largest core, can be achieved. The proposed approach has small hardware overhead and is easy to deploy. Only one LFSR, one phase shifter, and a few counters should be added to the SoC. The scheduling algorithm is also scalable for large industrial circuits. The CPU time for a large industrial design ranges from 1 to 30 minutes.