A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization

Authors:
Vikram Iyengar;Anshuman Chandra;Sharon Schweizer;Krishnendu Chakrabarty
Affiliations:
IBM Microelectronics;Duke University;Duke University;Duke University
Venue:
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2003

Citing 4
Cited 7

On Concurrent Test of Core-Based SOC Design

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Test Resource Partitioning for SOCs

IEEE Design & Test
Test Vector Compression Using EDA-ATE Synergies

VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization

VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium

InTeRail: A Test Architecture for Core-Based SOCs

IEEE Transactions on Computers
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling

Proceedings of the conference on Design, automation and test in Europe
Low-power multi-core ATPG to target concurrency

Integration, the VLSI Journal
Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Time-multiplexed compressed test of SOC designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test scheduling optimization for globally asynchronous locally synchronous system-on-chip using genetic algorithm

ICC'06 Proceedings of the 10th WSEAS international conference on Circuits

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Abstract

We integrate for the first time test access mechanism (TAM) optimization and test data compression into a single test methodology. We show how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test data volume and testing time. Two case studies using the integrated test architecture are presented.