Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems
ATS '99 Proceedings of the 8th Asian Test Symposium
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A Novel Strategy to Test Core Based Designs
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A low overhead design for testability and test generation technique for core-based systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast and low-cost testing technique for core-based system-chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 39th annual Design Automation Conference
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Computers
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints
Journal of Electronic Testing: Theory and Applications
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
FITS: An Integrated ILP-Based Test Scheduling Environment
IEEE Transactions on Computers
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
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In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objective for concurrent SOC test is to reduce test application time under the constraints of SOC pins and peak power consumption. The methodology used in this paper is not limited to any specific Test Access Mechanism (TAM). Additionally, it can also be applied to SOC budgeting at design phase to predict a tradeoff between test application time and SOC pins needed. The contribution of this paper is the formulation of the problem as a well-known 2-dimensional bin-packing problem. A best-fit heuristic algorithm is adopted to achieve optimal solution.