Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs
Journal of Electronic Testing: Theory and Applications
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Adaptive Test Scheduling in SoC's by Dynamic Partitioning
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Defect-Oriented Test Scheduling
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Scheduling and Scan-Chain Division under Power Constraint
ATS '01 Proceedings of the 10th Asian Test Symposium
Cluster-Based Test Architecture Design for System-on-Chip
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Multicriteria Optimization
Efficient BIST TPG design and test set compaction via input reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process
IEEE Transactions on Computers
An improved test access mechanism structure and optimization technique in system-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Abort-on-fail based test scheduling
Journal of Electronic Testing: Theory and Applications
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test environment for embedded cores-based system-on-chip (soc): development and methodologies
MIC'06 Proceedings of the 25th IASTED international conference on Modeling, indentification, and control
Towards Open Network-on-Chip Benchmarks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Power-aware SoC test planning for effective utilization of port-scalable testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe
The efficient TAM design for core-based SOCs testing
WSEAS Transactions on Circuits and Systems
An efficient scheduling algorithm based on multi-frequency tam for SOC testing
WSEAS Transactions on Circuits and Systems
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
IEICE - Transactions on Information and Systems
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling Tests for 3D Stacked Chips under Power Constraints
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract--We describe an integrated framework for system-on-chip (SOC) test automation. Our framework is based on a new test access mechanism (TAM) architecture consisting of flexible-width test buses that can fork and merge between cores. Test wrapper and TAM cooptimization for this architecture is performed by representing core tests using rectangles and by employing a novel rectangle packing algorithm for test scheduling. Test scheduling is tightly integrated with TAM optimization and it incorporates precedence and power constraints in the test schedule, while allowing the SOC integrator to designate a group of tests as preemptable. Test preemption helps avoid hardware and power consumption conflicts, thereby leading to a more efficient test schedule. Finally, we study the relationship between TAM width and tester data volume to identify an effective TAM width for the SOC. We present experimental results on our test automation framework for four benchmark SOCs.